The present invention relates to a method for making a planar array of independently connected electrical contact pads connected through multiple layers of conductive paths. There, are many applications for this type of device. For example, such a device may be used to provide a rectilinear array of pads for testing of ball grid array (BGA) modules or circuit boards with BGA interconnect patterns that are too small to be tested by conventional pin probe testers. Another application is to provide for interconnection to a similarly patterned array of independently connectable electrical contact pads in an electrically stimulated array. The requirement that the electrical contact pads be independently connectable creates a conductive path routing and cross-talk suppression challenge.
One use for a planar array of independently connectable electrical contact pads is for electrical stimulation of, and electrical reception from, an ultrasound array. For a more complete description of the requirements for a connector to an ultrasound array, please see U.S. Pat. No. 5,855,049, issued Jan. 5, 1999, which is hereby incorporated by reference as if fully set forth herein. As noted in this reference, it is typical to use a flex circuit electrical contact pad array for the purpose of electrically connecting an ultrasound array to take advantage of the acoustical and mechanical characteristics of a flex circuit. A flex circuit has enough flexibility to permit a full set of connections without suffering the effects of the gaps that can be created by slight nonuniformities between two rigid surfaces. In addition, the flex circuit can be flexibly routed to connect the array to external circuit boards or cabling.
Another use for an array of independently connectable electrical contact pads is for attachment to the terminals of an integrated circuit (IC) die. IC dies are typically produced having a set of terminals along the periphery of the die and with the terminals mutually spaced apart by 50 to 100 microns. The die is typically placed in a package to form an outside interconnect pitch of 1.27 mm or smaller, for connection to a PCB. The IC die terminals are typically connected to an intermediate chip scale package circuit by means of wire bonding or by flip chip mounting to a flex circuit that expands outwardly from the die perimeter to a larger rectilinear array. The principle reason why the IC die terminals are arranged solely along the perimeter of the IC die is because of the limitations of wire bonding and flex circuit manufacturing technology. If a flex circuit having a partial or full rectilinear array of interconnect pads with a pitch on the order of tens of microns could be efficiently produced, this would permit IC dies to be produced having terminals in a matching array, thereby permitting more terminals into and out of the IC, a highly desirable goal.
Yet another application for planar array of independently connectable electrical contact pads, is in the testing of PCBs. It is highly desirable to test a PCB after production but prior to connecting circuitry to the PCB. If a flaw in the PCB is discovered after circuitry has been connected to the PCB, the entire circuit must typically be discarded. For, a PCB having a tightly pitched array of terminals for connecting, to a ball grid array, however, it may be extremely difficult to form a test connector that independently contacts each one of these terminals. It would, therefore, be highly desirable to have a tightly packed planar array of independently connectable electrical contact pads for the purpose of forming a test connector for a PCB bearing tightly packed arrays of electrical contact pad contacts or to convert the tightly pitched array of terminals to a less tightly packed array which can be tested by conventional means. In addition, a tightly packed planar array of electrical contact pads can also be used to test the ball grid array IC circuit itself.
One method used to construct planar arrays of independently connectable electrical contact pads is known as the xe2x80x9cthin film/wet chemistryxe2x80x9d process of building up a flex circuit layer by layer. Each dielectric layer is spin coated on to the top of the previously created laminate structure, then drilled or etched, plated and patterned. For via interconnects, a pad is first formed on a deposited layer for connection to the prospective next layer to be deposited. After the next layer is deposited a blind via is drilled to the underlying pad, followed by platting and patterning of a pad directly over the via, forming an electrical connection to the pad below. The disadvantages of this method are that it is expensive and a mistake on any layer can ruin the entire flex circuit.
Another traditional method to construct planar arrays of independently connectable electrical contact pads has been to join together conductively patterned dielectric layers each having mutually co-located connective pads. Individual patterned dielectric layers are first bonded together, typically through an intermediate dielectric, followed by via drilling and plating through the mutually co-located electrical contact pad pads to connect one layer to the next. Typically the connective paths are patterned to allow through hole drilling to connect layers. As additional layers are added they are drilled and plated to form connections. There are two principle problems associated with this method. First, many process steps are involved to drill and plate the various layers. Second, the accuracy required to align the various layers and successfully drill and plate to connect them severely limits the array density. If through hole drilling instead of blind vias are used to connect layers, the traces must be routed so as to avoid drilling through traces running above or below the layer to be connected, further limiting the array density.
Yet an additional method of constructing an array of contact pads interconnected through a multilayer structure involves laminating patterned circuits together using anisotropic or z-axis adhesives which connect conductive portions of the individual layers together without forming a conductive short to neighboring traces. A disadvantage of this approach is the additional complexity involved in laying out the conductive circuit patterns as well as the higher cost and uncertain reliability of the anisotropic connective approach.
Although it theoretically might be desirable to adhere together a stack of layers bearing conductive paths to a top layer bearing an array of electrical contact pads and then drill and plate vias to connect each electrical contact pad to a target conductive path on an inner layer, a number of problems are presented in any attempt to implement such a method of construction. First, it is a challenge to drill through several layers without drilling through a conductor on a layer interposed between the drilling surface and the target conductive path. Second, some target conductive paths may be by necessity very thin, on the order of, microns, presenting a challenge to one attempting to accurately drill a via to the target conductive path. Our invention addresses these limitations as described below.
Those practicing photolithography face a number of problems. One problem is that of achieving accuracies of less than 25 microns due to the limitation on the degree to which the selectively masked light can be collimated (due to the physical size of the light source). In addition, for the sort of multilayer work described above, changes in layer size and shape due to shrinkage of a layer during processing, can be unpredictable and canbe only imperfectly addressed in the production of subsequent layers using a preset and unchangeable mask. Accordingly, adjacent layers may turn out to be mismatched. This potential mismatch must be taken into account in the design of the various layers, decreasing the density of features and the special efficiency of the design. Moreover, for short production runs, the production of a mask can add significantly to the overall production costs.
The present invention is a method of constructing a multilayer electric apparatus. The method includes forming a set of conductive features and a plurality of fiducial markings on a first dielectric layer in mutual reference to each other so that their relative positions are known to a first tolerance. Also, a pattern of information corresponding to a desired photoresist exposure pattern for a second layer of the multilayer electric apparatus is stored in a computer readable format. The locations of the fiducial markings on the first layer are measured and the pattern of information for the second layer is altered in correspondence to the measured locations of the fiducial markings. The updated pattern of information is used to control a laser to selectively expose the photoresist on the second layer. Finally, the first and second layers are joined to each other.
In a separate aspect, the present invention is a method of constructing a multilayer electric apparatus, comprising the steps of first providing a set of dielectric layers and forming a set of conductive features and at least one fiducial marking, in mutual reference to each other, on a first one of the dielectric layers. Next, the dielectric layers are joined together to form a stack, such that the first of the dielectric layers is interposed depthwise between others of the dielectric layers and the at least one fiducial marking is distinctly observable from outside of the stack. Finally, a via is drilled from the exterior of the stack to one of the conductive features of the first dielectric layer, referencing the drilling, to the fiducial marking.
In a further separate preferred aspect, the present invention is a method of constructing an electric apparatus, comprising the following steps. First, a set of dielectric layers is provided. Next, asset of conductive features and at least one fiducial marking are formed on a first one of the dielectric layers, in mutual reference to each other so that their relative positions are known to a first tolerance. Then, a set of pin holes is formed in each dielectric layer, each pin hole formed in relation to the fiducial marking for its dielectric layer and all of the sets of pin holes having a mutually identical placement. Finally the dielectric layers are arranged onto a pin fixture having a set of pins that match the mutually identical placement of the pin holes.